1. Field of the Invention
The present invention relates to a semiconductor memory and more particularly to a semiconductor memory device having a pad layout which consumes less chip area by jointly connecting transistors that are respectively connected to pads adjacent to each other.
The present application claims priority from Korean Application No. 7970/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Techniques for achieving high speed, high integration and low product cost of semiconductor memory devices is a continuing objective of the semiconductor memory industry. Miniaturization of semiconductor memory devices to achieve lower product cost has therefore become a key concern to manufacturers. However, since the number of pins increases as the capacity of a memory chip increases, a conventional pad layout necessarily increases die size.
Referring now to FIG. 1 showing a layout of an electrostatic discharge ESD protection transistor connected to a conventional address pad, it can be seen that ESD protection transistors 1 and 2 are respectively connected to address pads 9 and 10. The ESD protection transistor 1 has N-type active areas 3 and 4, which are formed to be separated from each other at a given interval T1 in a vertical direction. Source areas S1, S2, S3, S4 are formed in the N-type active areas 3 and 4. Drain areas D1 and D2 are respectively formed between the source areas S1 and S2 and areas S3 and S4. A gate G1 is formed on a channel area formed between the drain areas D1 and D2 and between the source areas S1 to S4. To instantaneously discharge a large amount of current in case a high voltage is applied through the drain areas D1 and D2 connected to the address pad 9, gate G1 has a wide width. In order to achieve better efficiency, active areas 3 and 4 are separated from each other at the given interval T1. Drain areas D1 and D2 and source areas S1 to S4 are areas into which N-type impurity ions of high density are injected. Gate G1 is symmetrically formed centering on drain areas D1 and D2.
The ESD protection transistor 2 is formed in the same manner as the ESD protection transistor 1 and includes a gate G2. The ESD protection transistor 1 is shielded by a P-type active guard line 5 for preventing latch up. The P-type active guard line 5 is then shielded by a N-type active guard line 6. Similarly, the ESD protection transistor 2 is shielded by a P-type active guard line 7. The P-type active guard line 7 is then shielded by a N-type active guard line 8. As described above, each of ESD protection transistors 1 and 2 is shielded by the corresponding P-type active guard lines 5,8, and has an N-type active area which includes a source area for each transistor. There is a disadvantage with this arrangement in that a large part of the area between the pads, like pads 9,6, is occupied by ESD